The present invention generally relates to the field of integrated circuits. More specifically, the present invention relates to wafer stacking for 3-dimensional integration.
Recently, there is increasing interest in the semiconductor industry to stack wafers, i.e. joining two or more wafers together, one on top (or underneath) the other. One of the more practical ways of bonding two wafers is by fusing copper structures on 2 wafers at high temperatures & external pressure. One area of difficulty preventing the accomplishment of quality stacking is the non-uniformity of the heights of copper structures relative to the dielectric (e.g. oxide), when copper structures are to be used to join the wafers together, and conventional chemical mechanical polishing (CMP) process is to be employed to create the copper structures.